(a) Field of the Invention
The present invention relates to a multilevel interconnection structure in a semiconductor device and, more particularly, to a multilevel interconnection structure having an air gap for insulating interconnects in the same layer. The present invention also relates to a method for manufacturing such a multilevel interconnection structure.
(b) Description of the Related Art
With the advance of finer pattern and higher operational speed of transistor elements in a semiconductor device, the line width and the line space in the interconnect pattern have been reduced remarkably. The reduction of the thickness of the semiconductor device, however, is not noticed partly because such a reduction is limited in view that a smaller interconnect in the thickness has a larger line resistance. As a result, parasitic capacitance between interconnects, especially in the same layer, tends to increase. For example, a current semiconductor device having a 0.35 .mu.m design rule MOSFET has a line space between layers on the order of 1 .mu.m, and has a line space between lines in the same layer on the order of 0.5 .mu.m, which means that the parasitic capacitance between interconnects in the same layer is dominant compared to that between layers in the current semiconductor device. In a next generation semiconductor device, wherein a finer space will be achieved between interconnects in the same layer with the line thickness being maintained, it is likely that the most of the component of the parasitic capacitance is attributable from the adjacent interconnects in the same layer. In this case, the semiconductor device will not effectively function due to its lower operational speed.
Patent Publication JP-A-7-326670 proposes a multilevel interconnection structure wherein an air void (air gap) is provided between adjacent lines in order to decrease the parasitic capacitance therebetween for improvement of the operational speed of the semiconductor device. Air has a lowest permittivity among known materials to thereby obtain a lower parasitic capacitance. FIGS. 1A to 1C show the process for fabrication of the multilevel interconnection structure having the air gap. In FIG. 1A, a first interlevel dielectric film 11 is formed on a semiconductor substrate 10, followed by formation of a first level interconnect layer 13 by using a selective etching technique. Next, as shown in FIG. 1B, a second interlevel dielectric film 18 made of silicon oxide exhibiting a poor deposition capability within through-holes is formed thereon by an atmospheric pressure CVD using monosilane and oxygen. The silicon oxide film 18 is grown to a large thickness, as shown in FIG. 1C, and involves an air void 19 within a small space between interconnects 13 due to the overhang of the silicon oxide film 18 itself. The resultant interconnects 13 have a smaller parasitic capacitance due to the air void 19.
In the technique as described above, however, it is generally difficult to control the parasitic capacitance with reproducibility due to the uncontrollable geometry of the air voids 19 which depend on the geometry of the interconnects 13 and therefore involve variation of the shape and size. The uncontrollable parasitic capacitance retards the optimum design for the circuit structure. In addition, the reduction of the parasitic capacitance is not sufficient because the silicon oxide 18 remaining between interconnects 13 raises the parasitic capacitance. Further, as shown in FIG. 2, if a through-hole overlaps with an air void 19a due to misalignment during selective etching of the first interlayer dielectric film 18, the air void 19a is also filled with metallic plug 22, which rather raises the parasitic capacitance. That is, this technique is substantially limited to a top dielectric layer or to the case of a sufficient margin for the etching.
Patent Publication JP-A-7-245301 proposes, for solving the above problem, a technique wherein an interlayer dielectric film made of carbon is deposited by CVD, followed by removal thereof by ashing. By this technique, parasitic capacitance is remarkably reduced because only an air gap is disposed between interconnects for insulation. The problem through-hole as described above will not arise if the ashing is carried out after fabrication of the contact plugs.
In this technique, however, the interconnects are supported only by the junctions or connections of the interconnects because the dielectric film between layers are substantially entirely removed, which raises another problem wherein interconnects are deformed by the absence of the intermediate support therefor. The deformation may cause an increase of the parasitic capacitance or a short-circuit failure. In addition, the metallic interconnects suffer from an insufficient radiation of heat generated during operation of the semiconductor device, which may accelerate electromigration of the metallic film. Further, since there is little etch-selectivity between current photoresist materials and the carbon film, this technique is not suited for a multilevel interconnection structure, wherein a plurality of etching steps are iterated.